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ADT7490
1
9
1
9
SCL
SDA
0
1
0
1
1
1
0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
FRAME 2
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADT7490
1
ACK. BY
ADT7490
ADDRESS POINTER REGISTER BYTE
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
FRAME 3
DATA BYTE
ACK. BY STOP BY
ADT7490 MASTER
Figure 18. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1
9
1
9
SCL
SDA
0
1
0
1
1
1
0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
FRAME 2
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADT7490
ACK. BY
ADT7490
ADDRESS POINTER REGISTER BYTE
STOP BY
MASTER
Figure 19. Writing to the Address Pointer Register Only
1
9
1
9
SCL
SDA
0
1
0
1
1
1
0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADT7490
FRAME 2
DATA BYTE FROM ADT7490
NO ACK. BY STOP BY
MASTER MASTER
Figure 20. Reading Data from a Previously Selected Register
It is possible to read a data byte from a data register
without first writing to the address pointer register if the
address pointer register is already at the correct value.
However, it is not possible to write data to a register without
writing to the address pointer register because the first data
byte of a write is always written to the address pointer
register.
In addition to supporting the send byte and receive byte
protocols, the ADT7490 also supports the read byte protocol
?
?
?
?
?
?
S: Start
P: Stop
R: Read
W: Write
A: Acknowledge
A: No acknowledge
The ADT7490 uses the following SMBus write protocols.
(see System Management Bus Specifications Rev. 2 for
more information; this document is available from the
SMBus organization).
If several read or write operations must be performed in
succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
Write Operations
The SMBus specification defines several protocols for
different types of read and write operations. The ones used
in the ADT7490 are discussed here. The following
abbreviations are used in the diagrams:
Send Byte
In this operation, the master device sends a single
command byte to a slave device, as follows:
1. The master device asserts a start condition on
SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and
the transaction ends.
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